A flash memory device employs a metal-oxide-semiconductor field effect transistor (MOSFET) having a floating gate which affects a threshold voltage Vt of the MOSFET. The flash memory device thus comprises a control gate which functions in the same manner as a normal gate of a conventional MOSFET and a floating gate which is separated from a channel of the MOSFET by a dielectric material, or a “floating gate dielectric,” but affects the operation of the MOSFET through control of the threshold voltage of the MOSFET. The charge stored in the floating gate is preserved even when a semiconductor chip is powered off. Thus, the flash memory device is a non-volatile memory device, and is typically referred to as an electrically erasable and programmable memory (EEPROM) device.
The floating gate stores a variable amount of charge which tunnels through the floating gate dielectric. A typical floating gate dielectric comprises a silicon oxide based material, e.g., silicon oxide or a stack of silicon oxide and silicon nitride. The amount of charge stored in the floating gate is dependent on bias conditions of the control gate, the drain, the source, and the body as well as the composition and thickness of the floating gate dielectric and the efficiency of charge trapping by the floating gate that is typically generated in the drain of the MOSFET by a hot, or energetic, charge carriers, i.e., hot electrons. The efficiency of charge trapping is a function of the degree of overlap of the floating gate with the drain of the MOSFET since the hot charge carriers are scattered in many directions from the drain. Typically, the floating gate is in one of the binary states i.e., a charged state and a discharged state. In the charged state, the floating gate stores a significant amount of charges, for example, electrons, to dispel electrons and attract holes in the channel of the MOSFET to alter the threshold voltage of the MOSFET. In the discharged state, the floating gate has an insignificant amount of charge, and effectively, does not alter the threshold voltage of the MOSFET. Thus, a binary bit of information may be stored in the form of electrical charges in the floating gate, and the binary bit of information may be read by measuring the threshold voltage of the MOSFET, typically by measuring the on-current of the MOSFET at a given bias condition.
In general, flash memory devices having a floating gate and a control gate on the same side of the channel of a MOSFET face difficulties in scaling of the gate dielectric since the gate dielectric is shared by the floating gate and the control gate. While it is advantageous to employ a thinner gate dielectric to enhance performance of the MOSFET, such reduction in the thickness of the gate dielectric tends to increase leakage of charge from the floating gate. In practice, there is an optimum gate dielectric thickness for the floating gate, and indefinite scaling of the gate dielectric is not desirable for the floating gate.
U.S. Pat. No. 6,445,032 to Kumar et al. discloses a prior art flash memory device employing a planar MOSFET. A control gate is formed on a control gate dielectric located on one side of the channel, while a floating gate is formed on a floating gate dielectric located on the back side of the MOSFET, i.e., on the opposite side of the channel. Thus, the control gate dielectric may be scaled to enhance performance of the planar MOSFET, while the thickness of the floating gate dielectric is set at an optimal thickness. However, it is difficult to form self-aligned double gate flash device with a structure of a planar MOSFET.
Fin metal-oxide-semiconductor field effect transistor (FinMOSFET) is an emerging technology which provides solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at, and below, the 45 nm node. FinMOSFET structures include fin field effect transistors (finFETs), which comprise at least one narrow (preferably <30 nm wide) semiconductor fin gated on at least two opposing sides of each of the at least one semiconductor fin. Preferred prior art finFET structures are formed on a semiconductor-on-insulator (SOI) substrate, because of low source/drain diffusion to substrate capacitance and ease of electrical isolation by shallow trench isolation structures.
In a finFET, a gate electrode located on at least two sides of the channel of the transistor is a common feature of finFETs known in the art. Due to the advantageous feature of full depletion in a finFET, the increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device has faster switching times, equivalent or higher current density, and much improved short channel control than the mainstream CMOS technology utilizing similar critical dimensions.
In a typical finFET structure, at least one horizontal channel on a vertical sidewall is provided within the semiconductor “fin” that is set sideways, or edgewise, upon a substrate. Typically, the fin comprises a single crystalline semiconductor material with a substantially rectangular cross-sectional area. Also typically, the height of the fin is greater than width of the fin to enable higher on-current per unit area of semiconductor area used for the finFET structure. In order to obtain desirable control of short channel effects (SCEs), the semiconductor fin is thin enough in a device channel region to ensure forming fully depleted semiconductor devices. Typically, the thickness, or the horizontal width, of a fin in a finFET is less than two-thirds of its gate length in order to obtain good control of the short channel effect.
Employment of finFETs in semiconductor devices requires different semiconductor processing steps than planar FETs, and therefore, a flash memory device having a manufacturing sequence that is compatible with a manufacturing sequence of finFETs is needed. U.S. Pat. No. 7,087,952 to Zhu et al., provides a prior art flash memory device employing a semiconductor fin, thus providing a non-volatile programmable memory that is compatible with finFET devices. However, the prior art device according to Zhu et al. employs the same gate lengths for both control and floating gates. Thus, it is difficult to form a structure having a larger overlap capacitance on the floating gate than on the control gate, and in general, it is difficult to form a structure having different overlap capacitance between the control and the floating gate. In other words, a structure having the same gate length for the control gate and the floating gate is not conducive for charging and discharging of the floating gate as needed in a non-volatile memory.
In view of the above, there exists a need to provide a finFET based flash memory device structure having a control gate that may be scaled independently from a floating gate.
Therefore, there exists a need to provide a finFET based flash memory device structure having an extended overlap between a drain of the finFET and a floating gate.